1. Field of the Invention
The invention relates to flash memories, and more particularly to a control device and a method for extending data retention and improving data reliability of storage units of flash memories.
2. Description of the Related Art
A non-volatile memory is widely used in a plurality of applications, such as solid-state disks (SSD), memory cards, digital cameras, multi-media displayers, cell phones, computers, and other electronic devices.
Referring to FIG. 1A, a circuit diagram of memory cells of a flash memory is shown. Referring to FIG. 1B, a schematic diagram of charge density of a flash memory is shown. A single-level-cell (SLC) flash memory comprises a memory cell array comprising a plurality of memory cells. The control gates of a plurality of memory cells located at a single line are coupled to a word line (WL). The sources and drains of a plurality of memory cells located at a single column are coupled together to form a bit line (BL). The memory cells further comprises floating gates for charge storage, and the charge stored in the floating gates does not disappear after a power supply is disconnected.
To determine digital data stored in the memory cells, the charge density distribution of the memory cells is determined. For example, if the charge density of the memory cell 11 is between the levels a and b shown in FIG. 1B, and a measure voltage Vd+ is added to the word line WL1, a current then passes through the bit line BL1, and the data bit stored in the memory cell 11 has a value of “1”. Otherwise, if the charge density of the memory cell 12 is between the levels b and c shown in FIG. 1B, a current does not pass through the bit line BL2, and the data bit stored in the memory cell 12 has a value of “0”.
A patent application with publication no. US 2011/0138111 A1 discloses a flash memory, wherein 2 data bits are determined according to charge density distribution of memory cells of the flash memory. The difference of the circuit structure between the flash memory and a conventional SLC flash memory is that the flash memory is sequentially measured according to the voltages Vd+, Vd1+, and Vd2+, and four sets of 2 data bits of (11, 10, 00, 01) are determined from one memory cell. The flash memory is referred to as a multi-level-cell (MLC) flash memory. A triple-level-cell (TLC) flash memory further determines eight sets of 3 data bits of (111, 110, 100, 101, 001, 000, 010, 011) from one memory cell.
The TLC flash memory has a higher data capacity than those of the MLC flash memory and the SLC flash memory. Because the width of the charge distribution of the memory cell of the SLC flash memory is double that of the MLC flash memory and four times that of the TLC flash memory, the SLC flash memory has a smaller measurement error, a higher access speed, and a better data reliability than the MLC flash memory and the TLC flash memory. In other words, the MLC flash memory and the TLC flash memory have lower manufacturing costs than that of the SLC flash memory but have shorter endurance and smaller wear capacity than that of the SLC flash memory.
The conventional flash memory device therefore cannot have all the benefits of a low manufacturing cost, high data capacity, long endurance, and high wear capacity.